Re: [myhdl-list] ROMs and Init'd RAMs

[Christopher F. <chr...@gm...>]

<snip>
>>
>> The above will not work with ROM extraction but appears to work with RAM
>> extraction, but RAM extraction requires initial values (only applicable
>> for FPGAs and not currently implemented) or some method to program the
>> RAM with the initial values.
>
> Using a singal (probably declared as constant) which has initialvalues is
> to my knowledge the number
> one way to describe some indexable constants in VHDL. I dont think the
> switch case construct which maps the values is
> in any way preferable to that other than for the Xilinx tool ROM inference.
>
> It is a very basic way to describe some constant values in VHDL. If a tool
> doesn't support this i personaly would not use
> it. If there is no ROM or RAM for the device for which the synthesis is
> done the tool should at least could implement your constant signals with
> some Vcc or Ground connections wheater it is for an ASIC or an FPGA. Realy
> if the tool can't do this, its game over.
<snip>

We have had a couple threads on this and I created a wiki
page [1] to keep track of the /initial value support/ progress,
comments, and opinions.  The ROM/RAM is closely related
(pre-init ram).  I think the biggest hurdle is resolving
the options for automatic memory synthesis, mainly for FPGAs,
that may not map to other synthesis technologies.

Currently, the /case/ statements for ROM will work in any
technology but will only be an optimized memory structure
in the Xilinx tools.  The Altera tools will not extract a ROM.
It has been requested that initial values for list of signals
be created.  The FPGA tools (at least Altera) creates a
configuration file to pre-init the BRAMs.

We had discussed adding function attributes for conversion
configuration.  We discussed adding an attribute to disable
initial value creation.

   toVerilog.disable_init
   toVHDL.disable_init

I believe, but I didn't list it in the wiki, we also discussed
adding an attribute to enable list of signals initial values.

   toVerilog.enable_list_init
   toVHDL.enable_list_init

If this makes sense, I believe we have the options covered.
The tuple of ints will be converted as is, and a list of signals
can be configured to create the array (list of signals) initial
values using the VHDL function and Verilog initial block as
previously discussed.

Regards,
Chris

[1] http://www.myhdl.org/doku.php/dev:initial_values