Re: [myhdl-list] Conversion for variable argument list

[Jan D. <ja...@ja...>]

On 07/18/2012 02:23 PM, Oscar Diaz wrote:
> Hi
>
> Suppose I want to design a cascade adder of several number of inputs,
> for instance, a 3-input adder consists of two 2-input adders connected
> in cascade, a 4-input adder will have three 2-input adders, and so on.
> The tricky part is I won't know the number of inputs I need until
> runtime.
>
> It really doesn't matter for me how to implement it internally, my
> problem is how to declare the argument list to accept a "variable
> number" of input values, and I would like a VHDL (or Verilog) code
> that reflects the correct number of inputs.
>
> My first approach was to use variable argument list:
>
> def variable_adder(output, *inputs):
>
> Works fine for simulation, fails for conversion.

Only if it's at the top-level, which is probably not
how you will use it in a real design.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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