[myhdl-list] Conversion for variable argument list

[Oscar D. <osc...@gm...>]

Hi

Suppose I want to design a cascade adder of several number of inputs,
for instance, a 3-input adder consists of two 2-input adders connected
in cascade, a 4-input adder will have three 2-input adders, and so on.
The tricky part is I won't know the number of inputs I need until
runtime.

It really doesn't matter for me how to implement it internally, my
problem is how to declare the argument list to accept a "variable
number" of input values, and I would like a VHDL (or Verilog) code
that reflects the correct number of inputs.

My first approach was to use variable argument list:

def variable_adder(output, *inputs):

Works fine for simulation, fails for conversion. I'm wonder if there's
any way to dynamically declare the component interface, or if there's
a better idea to dynamically instantiate components (I really don't
like the idea of declare each one of "variable_adder2",
"variable_adder3", etc. in MyHDL).

In case of this approach are proved wrong, I already though on some
workarounds for this precise example:

1. Put a fixed number of inputs (say 10 for example) and ignore unused
inputs that will be trimmed in synthesis stage.
2. Put a single input bit_vector and slice it internally depending on
number of inputs (this idea is my best bet).

My intention is to see if the idea of elaboration can be applied (or
if it make sense) to the signal interface.

I attach a example with the tests I've been working on.

Best regards

-- 
Oscar Díaz
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