[myhdl-list] No proper edge value test

[Christopher F. <chr...@gm...>]

With the latest 0.8dev code the following will cause
a "No proper edge value test"

     def testm(clock, reset, out):
         @always(clock.posedge, reset.negedge)
         def hdl():
             if not reset:
                 out.next = 0
             else:
                 out.next = out ^ 0x55

         return hdl

    def convert():
        clock = Signal(False)
        reset = Signal(False)
        out   = Signal(intbv(0)[8:])
        toVerilog(testm, clock, reset, out)
        toVHDL(testm, clock, reset, out)


Is this expected behavior?  This could possibly break
existing code.

Regards,
Chris