Re: [myhdl-list] Architecture Modelling with MyHDL

[Christopher F. <chr...@gm...>]

<snip>
>>
>>
>>      We can now perform pretty complicated concurrent simulations with this
>>      circular buffer, such as connect each side to a different clock - as
>>      demonstrated in the attached test.py.
>
> This is probably quite obvious so please forgive me if this question
> is very basic. I don't understand how can you directly call
> "super(HCBuff, self).write(din.val)", since in the original write
> method self.wr_off is incremented directly, rather than using
> self.wr_off.next (which is not possible since self.wr_off is not a
> signal). A similar problem occurs with the read method.
>
> What am I missing?
>
> Angel
>

In this case the two instance variables wr_off and rd_off
don't need to be signals (they don't signal anything) they
are just local variables that keep track of some state.
The only time super(CBuff,self).write and super(CBuff,self).read
do something is when they are explicitly called.

The example takes an "algorithm" and then wraps an interface
that looks like a module, in this case the interface is
a clock and data.  As mentioned, this is good for a "golden"
models.  You can verify the "algorithm" via standard
imperative programming, write, read, write, write, read.  You
have a set of statements you can see what happens.  And then
you can add the interface adapters to get a cycle accurate
model and compare the actual implementation to the "golden" model.

Regards,
Chis