Re: [myhdl-list] Architecture Modelling with MyHDL
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From: Angel E. <ang...@gm...> - 2012-07-09 20:32:09
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On Mon, Jul 9, 2012 at 9:45 PM, Uri Nix <ur...@gm...> wrote: > Hi all, > > I would like to focus a bit on MyHDL's modelling abilities, using a > simple > example to demonstrate an effective development flow. > > Let's consider a circular buffer, implemented as a pure algorithm. > > class CBuff(object): > def __init__(self, size): > self.ram = array.array('B', [0]*size) > self.modulo = size > self.rd_off = 0 > self.wr_off = 0 > > def write(self, value): > self.ram[self.wr_off] = value > self.wr_off += 1 > if self.wr_off >= self.modulo: self.wr_off = 0 > > def read(self): > value = self.ram[self.rd_off] > self.rd_off += 1 > if self.rd_off >= self.modulo: self.rd_off = 0 > return value > > > After fully testing this algorithm, we can add a measure of hardware > orientation by making the accesses synchronous (using the same method > names, but that of course is a matter of taste): > > class HCBuff(CBuff): > def write(self, clk, din): > @always(clk.posedge) > def logic(): > super(HCBuff, self).write(din.val) > return logic > > def read(self, clk, dout): > @always(clk.posedge) > def logic(): > dout.next = super(HCBuff, self).read() > return logic > > > We can now perform pretty complicated concurrent simulations with this > circular buffer, such as connect each side to a different clock - as > demonstrated in the attached test.py. This is probably quite obvious so please forgive me if this question is very basic. I don't understand how can you directly call "super(HCBuff, self).write(din.val)", since in the original write method self.wr_off is incremented directly, rather than using self.wr_off.next (which is not possible since self.wr_off is not a signal). A similar problem occurs with the read method. What am I missing? Angel |