[myhdl-list] Architecture Modelling with MyHDL

[Uri N. <ur...@gm...>]

Hi all,

    I would like to focus a bit on MyHDL's modelling abilities, using a
simple
    example to demonstrate an effective development flow.

    Let's consider a circular buffer, implemented as a pure algorithm.

class CBuff(object):
    def __init__(self, size):
        self.ram = array.array('B', [0]*size)
        self.modulo = size
        self.rd_off = 0
        self.wr_off = 0

    def write(self, value):
        self.ram[self.wr_off] = value
        self.wr_off += 1
        if self.wr_off >= self.modulo: self.wr_off = 0

    def read(self):
        value = self.ram[self.rd_off]
        self.rd_off += 1
        if self.rd_off >= self.modulo: self.rd_off = 0
        return value


    After fully testing this algorithm, we can add a measure of hardware
    orientation by making the accesses synchronous (using the same method
    names, but that of course is a matter of taste):

class HCBuff(CBuff):
    def write(self, clk, din):
        @always(clk.posedge)
        def logic():
            super(HCBuff, self).write(din.val)
        return logic

    def read(self, clk, dout):
        @always(clk.posedge)
        def logic():
            dout.next = super(HCBuff, self).read()
        return logic


    We can now perform pretty complicated concurrent simulations with this
    circular buffer, such as connect each side to a different clock - as
    demonstrated in the attached test.py.


    This methodology allows a very graceful transition from pure algorithms
to
    hardware oriented structures. Indeed, when considering the design phases
    detailed in Jan's article
    [http://www.jandecaluwe.com/hdldesign/digmac.html], the delivery of the
    architectural stage can very well be the verification model - already
    validated against the original concept!


    I have found this aspect of MyHDL very powerful and amazingly easy even
    for more complicated structures. Hopefully this can gain more users from
    the non-RTL oriented.

Cheers,
    Uri