Re: [myhdl-list] Reset functionality "synthesis"

[Christopher F. <chr...@gm...>]

On 7/5/12 11:28 AM, Tom Dillon wrote:
>
> On 07/05/2012 10:50 AM, Angel Ezquerra wrote:
>> On Thu, Jul 5, 2012 at 5:27 PM, Jan Decaluwe <ja...@ja...> wrote:
>>> On 07/04/2012 09:21 PM, Christopher Felton wrote:
>>>
>>>> I'm getting to this conversation a little late.  It sounds
>>>> like we decided explicitly listing the /level/ and /async/
>>>> is preferred.  I am ok with this.
>>> I think that's how it's going to be.
>>>
>>>>    If it wasn't enforced
>>>> (I am ambivalent if is should be enforced) I would adopt
>>>> the style to always list, I like how it looks.
>>>>
>>>>             reset = ResetSignal(0, level=False, async=True)
>>> Make that 'active' instead of 'level', e.g. active=LOW
>>>
>>>> I use the common async assert, sync release type resets,
>>>> as well.
>>>>
>>>> With the /always_seq/ something that might be worth discussing
>>>> is the inclusion of clock gating.  Clock gating is used
>>>> frequently in ASIC designs and is becoming more common in
>>>> FPGA designs.  A clock gating description might look like the
>>>> following with the original @always construct.
>>>>
>>>>             @always(clock.posedge, reset.negedge)
>>>>             def hld():
>>>>                 if not reset:
>>>>                     ...
>>>>                 else:
>>>>                     if(enable) :  # clock gate signal
>>>>                         x.next = somethingAwesome or somethingGreat
>>> I guess the intention is that dff's with enables are inferred
>>> when available. We should find out what the exact templates are
>>> in Verilog and VHDL that support this e.g. probably the enable
>>> condition should be and'ed with the clock edge condition in
>>> VHDL.
>> I believe that if you do "if enable = '1' then" right after your "if
>> rising_edge(CLK) then" Xilinx ISE will properly infer the clock
>> enable. I can confirm it tomorrow.
>
> That would work if we are talking about trying to use the clock enable
> on the DFFs. But when I hear clock gating that makes me think you are
> trying to actually stop the clock to the DFF? Could be to save power?
>
> The synthesis tools try hard to utilize the clock enable inputs.
>

Yes, clock gating is used to reduce dynamic power consumption.
Clock gating is too low-level of a description it should
be modeled as an enable.  I should have simply said a clock
enable and not clock gating.  How the enable is implemented
is technology dependent.  Functionally, a FF with a clock
enable, an input mux, or clock gate should all act the same.
Synthesis settings can decide how the enable is implemented.

I am having been having second thoughts if this is really useful
with the /@always_seq/ decorator.  It only removes 1 line in
the current /@always_seq/, maybe it is not as beneficial as the
reset.

Regards,
Chris