Re: [myhdl-list] Reset functionality "synthesis"

[Tom D. <td...@di...>]

On 07/04/2012 04:05 AM, Jan Decaluwe wrote:
> On 07/04/2012 07:57 AM, Angel Ezquerra wrote:
>
>> Particularly, on section "Use of Resets and Performance" it describes
>> why synchronous reset should be used. It summarizes its advice as
>> follows:
>>
>> "Avoid asynchronous reset because it prevents packing of registers
>> into dedicated
>> resources and affects performance, utilization, and tool optimizations."
> I believe what is what Xilinx is doing here is pushing its own
> problem to designers. Of course I understand that using a synchronous
> reset or no reset can result in a more "optimal" design.
> What I don't understand is why a synthesis tool wouldn't be able
> to prove that some resets in dedicated resources are unnecessary,
> e.g. in a shift register.

Aren't we just talking about the default case? I will still be able to 
use no reset if I prefer?