Re: [myhdl-list] Reset functionality "synthesis"

[Jan D. <ja...@ja...>]

On 07/04/2012 09:21 PM, Christopher Felton wrote:

>>
>
> I'm getting to this conversation a little late.  It sounds
> like we decided explicitly listing the /level/ and /async/
> is preferred.  I am ok with this.

I think that's how it's going to be.

>  If it wasn't enforced
> (I am ambivalent if is should be enforced) I would adopt
> the style to always list, I like how it looks.
>
>           reset = ResetSignal(0, level=False, async=True)

Make that 'active' instead of 'level', e.g. active=LOW

> I use the common async assert, sync release type resets,
> as well.
>
> With the /always_seq/ something that might be worth discussing
> is the inclusion of clock gating.  Clock gating is used
> frequently in ASIC designs and is becoming more common in
> FPGA designs.  A clock gating description might look like the
> following with the original @always construct.
>
>           @always(clock.posedge, reset.negedge)
>           def hld():
>               if not reset:
>                   ...
>               else:
>                   if(enable) :  # clock gate signal
>                       x.next = somethingAwesome or somethingGreat

I guess the intention is that dff's with enables are inferred
when available. We should find out what the exact templates are
in Verilog and VHDL that support this e.g. probably the enable
condition should be and'ed with the clock edge condition in
VHDL.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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