Re: [myhdl-list] Reset functionality "synthesis"

[Dan W. <eti...@gm...>]

On Wed, Jul 4, 2012 at 6:46 AM, Jan Decaluwe <ja...@ja...> wrote:
> On 07/04/2012 11:27 AM, Angel Ezquerra wrote:
>> On Wed, Jul 4, 2012 at 11:05 AM, Jan Decaluwe<ja...@ja...>  wrote:
>>> On 07/04/2012 07:57 AM, Angel Ezquerra wrote:
>>> Yes, I can see that point. And of course, we can turn the whole
>>> thing to our advantage by showing that you can switch between the
>>> various styles without changing the code, by merely changing the
>>> reset constructor.
>>
>> That is a very good point.
>
> I start to like it. By require explicit settings, we draw attention
> to the fact that it is trivial to support various schemes, in
> contrast to current art. A marketing decision, as it were :-)


Don't do much FPGA work here, but the explicit specification for the
ResetSignal constructor would keep the code more clear; this
especially since the active state is no longer specified directly in
the @always block as before.

I like the active low default, but not "hiding" the exact desired
reset behavior and throwing an exception seems the pythonic way.

Dan


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