Re: [myhdl-list] Reset functionality "synthesis"
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jandecaluwe
From: Jan D. <ja...@ja...> - 2012-07-04 09:05:40
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On 07/04/2012 07:57 AM, Angel Ezquerra wrote: > Particularly, on section "Use of Resets and Performance" it describes > why synchronous reset should be used. It summarizes its advice as > follows: > > "Avoid asynchronous reset because it prevents packing of registers > into dedicated > resources and affects performance, utilization, and tool optimizations." I believe what is what Xilinx is doing here is pushing its own problem to designers. Of course I understand that using a synchronous reset or no reset can result in a more "optimal" design. What I don't understand is why a synthesis tool wouldn't be able to prove that some resets in dedicated resources are unnecessary, e.g. in a shift register. As for synchronous reset, my question remains: what if your system is such that you don't have reliable clocks during power-on-reset? Altera agrees, because they document the scheme I described as "preferred when designing an FPGA circuit" here: http://www.altera.com/literature/hb/qts/qts_qii51006.pdf > As for the technique that you described to use an asynchronous reset > whose deassert is synchronous with the clock, I'm unsure how that > would work with a Xilinx FPGA. In our system we have an external, > asynchronous (by definition) signal which we register on each our our > clock domains, converting it into a synchronous signal which we use as > a synchronous reset. So the global reset is asynchronous, but the > different module resets are synchronous. Here is an article from a Xilinx application engineer that describes that technique exactly. It seems Xilinx has caught up with the real world :-) http://www.eetimes.com/design/programmable-logic/4218673/How-do-I-reset-my-FPGA- > So I personally would make both the reset type and the active high/low > settings explicit. Given that as you said this will probably be done > only once I think it would probably even make the code more readable. Yes, I can see that point. And of course, we can turn the whole thing to our advantage by showing that you can switch between the various styles without changing the code, by merely changing the reset constructor. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |