Re: [myhdl-list] Reset functionality "synthesis"

[Angel E. <ang...@gm...>]

On Tue, Jul 3, 2012 at 11:04 PM, Jan Decaluwe <ja...@ja...> wrote:
> On 07/03/2012 08:45 PM, Jan Decaluwe wrote:
>> On 07/03/2012 06:40 PM, Angel Ezquerra wrote:
>>
>>>
>>> Jan,
>>>
>>> given how contentious the asynchronous vs synchronous reset debate is
>>> I would argue that there should be no default value in this case, and
>>> that the reset type should always be set explicitly.
>>
>> I am quite surprized by this, is this really so contentious?
>> In my whole career as a design engineer, I don't recall one
>> single incident about this (many about other issues :-)).
>>
>> Actually, I have *always* used the mixed approach, where you
>> go into reset asynchronously, but come out of it synchronously.
>> In this method, the reset driver comes out of a ff that
>> is reset asychronously with the primary reset, and that
>> also synchronizes the primary reset.
>>
>> For this to work, the ffs in the design should have
>> an asynchronous reset, but that doesn't mean the
>> reset scheme itself is asynchronous, as described.
>> The big advantage of this method is that you don't
>> need the clock to be present to go into reset,
>> only to come out of it. So you avoid power-up issues
>> with clocks and pll's.
>>
>> I thought this was the standard practice, which is why
>> I intuitively made it the default.
>>
>> I'd like to hear more opinions.
>
> One more point: if the style is explicit, I think the
> active level should be also, for consistency. One could
> argue that it's not that bad, only once as opposed to
> scattered through the code as currently.
>
> But then again, I would think that active low and
> asynchronous covers 99% of the practical cases ...
> or not?
>
> Undecided.
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com

That is actually not right for Xilinx FPGAs. The Xilinx manuals
actually encourage you to use active high reset because "the SR
control port on Xilinx registers is active high. If the RTL code
describes active-low set / reset / preset / clear functionality, the
synthesis tool will infer an inverter before it can directly drive the
control port of a register. You must accomplish this inversion with a
lookup table, thus taking up a LUT input. The additional logic that
active-low control signals infers may lead to longer runtimes and
result in poorer device utilization. It will also affect timing and
power."

As for the asynchronous vs synchronous reset, I suggest you guys have a look at:
http://www.xilinx.com/support/documentation/white_papers/wp231.pdf

Particularly, on section "Use of Resets and Performance" it describes
why synchronous reset should be used. It summarizes its advice as
follows:

"Avoid asynchronous reset because it prevents packing of registers
into dedicated
resources and affects performance, utilization, and tool optimizations."

As for the technique that you described to use an asynchronous reset
whose deassert is synchronous with the clock, I'm unsure how that
would work with a Xilinx FPGA. In our system we have an external,
asynchronous (by definition) signal which we register on each our our
clock domains, converting it into a synchronous signal which we use as
a synchronous reset. So the global reset is asynchronous, but the
different module resets are synchronous.

So I personally would make both the reset type and the active high/low
settings explicit. Given that as you said this will probably be done
only once I think it would probably even make the code more readable.

Cheers,

Angel