Re: [myhdl-list] Incorrect conclusions in TSConIT paper

[Christopher F. <chr...@gm...>]

On 6/30/12 2:11 PM, Norbo wrote:
> def firfilt(sig_in, sig_out, coef, clk):
>            bufferVal = [Signal(intbv(0, min=sig_in.min, max=sig_in.max))
> for ii in range(len(coef))]
>            coefs = [Signal(intbv(ii, min=min(coef), max=max(coef)+1)) for
> ii in coef]
>            mshift = len(sig_in)-1
>            @always(clk.posedge)
>            def hdl_sop():
>              sop = (bufferVal[0] * coefs[0])
>              # Note this adds an extra delay! (Group delay N/2+2)
>              bufferVal[0].next=sig_in
> 	
>              for ii in range(len(coef)-1):
>                 bufferVal[ii+1].next = bufferVal[ii]
>                 sop = sop + (bufferVal[ii+1] * coefs[ii+1])
>              sig_out.next = (sop >> mshift)
>
>            return hdl_sop


It should be noted, that the above doesn't work with any current version 
of code.  I think you (Norbo) might have some local changes to create 
the initial values for a RAM and they probably will be added with the 
initial value changes but there are a bunch of tools that need to be 
tested/verified.

The above will not work with ROM extraction but appears to work with RAM 
extraction, but RAM extraction requires initial values (only applicable 
for FPGAs and not currently implemented) or some method to program the 
RAM with the initial values.

Regards,
Chris