Re: [myhdl-list] Incorrect conclusions in TSConIT paper

[Christopher F. <chr...@gm...>]

<snip>
>
> My version with the initial values would look like this:
>
>     def firfilt(sig_in, sig_out, coef, clk):
>         bufferVal = [Signal(intbv(0, min=sig_in.min, max=sig_in.max)) for ii
> in range(len(coef))]
>         coefs = [Signal(intbv(ii, min=min(coef), max=max(coef)+1)) for ii in
> coef]
>         mshift = len(sig_in)-1
>         @always(clk.posedge)
>         def hdl_sop():
> 	  sop = 0
> 	  # Note this adds an extra delay! (Group delay N/2+2)
> 	  bufferVal[0].next=sig_in
> 	  for ii in range(len(coef)-1):
> 	      bufferVal[ii+1].next = bufferVal[ii]
> 	      sop = sop + (bufferVal[ii] * coefs[ii])
> 	  sig_out.next = (sop >> mshift)
>
>         return hdl_sop
>
> but there is still the shift error.
>
>
> greetings
> Norbo
>
>

I don't think the above would work because the loop doesn't use 
bufferVal[len(coef)-1) and coef[len(coef)-1].  I think if you ran the 
testbench it would fail?  If the testbench does pass, I think my test 
conditions are not tight enough then, disregarding the last tap and 
coefficient should have some effect.  I believe you either need the 
conditional or two loops.  Given the original context, I used the 
conditional vs. an /if/ or two loops.

Regards,
Chris