Re: [myhdl-list] Lists of signals now do appear in vcd file
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From: Jan D. <ja...@ja...> - 2012-06-27 21:41:29
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On 06/27/2012 08:14 PM, Christopher Felton wrote: > On 6/27/2012 12:15 PM, Jan Decaluwe wrote: >> I am considering to incorporate this feature more >> or less as per this patch. >> >> I don't want to create a different function - this >> could be a configuration of traceSignals. >> >> One question: should I make memory tracing optional? >> Or is it something that people just will always >> want to use when available? >> >> Jan >> >> > > I vote always on. > > If it were to be optional, I believe the use case is when modeling large > memories. For a larger memory you might not want the overhead. In this > case I would want a method to disable only for a particular LoS and not > all LoS. My main use case for LoS is not to model RAM or ROM but for > modularity. I have implemented it such that it is on by default, and controlled by setting 'traceSignals.tracelists'. Only in 0.8-dev, this qualifies as a new feature instead of a bug. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |