Re: [myhdl-list] Simplifying Interfaces

[Christopher F. <chr...@gm...>]

On 6/22/2012 10:24 AM, Jan Decaluwe wrote:
> Hi:
>
> I don't follow the example completely, but if you  -
> an experienced MyHDL designer - are surprized, then
> others will be even more so.
>
> I wonder if we can come up with an example suited for
> the MyHDL by Example section, that demonstrates the power
> of these techniques.
>
> The message should be that conversion only deals with
> code inside generators, in the context of their namespaces.
> Conversion restrictions only apply to that code.
> The namespaces are created during elaboration, so it
> doesn't matter how.
>

I have been trying to think of a good example, an example that isn't too 
large (too much code to dig through for a cookbook example) and an 
example that fits nicely, I haven't come up with too many ideas.

One example that appears to be used heavily with VHDL records and SV 
structs is a simple {opcode, address, flags} bundling.  But this example 
on its own wouldn't be functional, it wouldn't do anything.

It would be nice to have a small example that does something, I am 
failing to think of a good example.

Anyone else have an idea for an example?  I think for the example to be 
useful, you would want a design that you would use multiple modules and 
have some interface between.  But the interface would be small (limited 
number of signals in the class) so the the example would be digestible.

Regards,
Chris