Re: [myhdl-list] Simplifying Interfaces

[Christopher F. <chr...@gm...>]

On 6/25/2012 3:30 AM, Wesley New wrote:
> Firstly, thanks for Chris for bringing this feature to light. It is
> definitely one I will employ.
>
> The only problem I am having is that the ports arent expanded out when I am
> using user-defined hdl.
> As it isnt creating a flat file, the wrapper doesnt have any wishbone ports.
>
> For instance see the attached file.
>
> Initially all I wish to do is to encapsulate the wishbone ports so that I
> dont have to type them every time I instantiate a module that has a
> wishbone interface
>
> Regards
>
> Wesley
>


You would not be able to use the "object" on the top-level.  The outside 
world (your Verilog or VHDL) wouldn't know how to interface to a /wb/. 
The top-level has to be the discrete signals everything inside can use 
the /wb/ to simplify the interface.

I haven't tested it with the user defined code, you might have to do and 
extra step, but it should be possible.

Regards,
Chris