Re: [myhdl-list] Reset functionality "synthesis"

[Jan D. <ja...@ja...>]

On 06/15/2012 04:39 PM, Tom Dillon wrote:
> One question, will you still be able to have a register that is not
> reset and doesn't have an initial value?
>
> I often use those in FPGAs when I want a shift register to get
> optimized to local memory.

For clarity: the present proposal suggest to use initial
values in MyHDL as a specification of reset values.
This is completely independent from the question whether
such initial values should be written out in the converted
Verilog or VHDL output code.

The proposal would not change any current feature. Everything
you can do today would be available unchanged. What you
would have is an additional decorator that can be used
to infer the reset structure automatically.

Even if you don't want a reset, the new decorator would
have value, because it permits to specify the absence
of a reset explicitly:

     always_ff(clock.posedge, reset=None)
     def shift_reg():
         reg.next = reg << 1

A reviewer would have no doubt that the absence of the
reset is intentional, instead of a potential oversight.

What you would not be able to do with this decorator
is to mix resettable and non-resettable registers in the
same block. But in my view that is not a good idea style-wise
anyway. I always factor out such registers in a separate block.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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