Re: [myhdl-list] Summary of "Intial Values Support" threads

[Jan D. <ja...@ja...>]

On 05/30/2012 06:47 AM, Christopher Felton wrote:
> We listed a summary a couple time but the initial value support (ivs)
> was embedded in a separate thread.  So, I thought it would be worth
> while to summarize in a new thread.
>
>
>     1.  Initial value support can be re-enabled.  The Verilog
>         support of initial values as verified with the latest
>         of Quartus.
>         Need to test with (list syn and sim tools)?
>           [x] Quartus latest
>           [ ] ISE (xst) latest
>           [ ] cver
>           [ ] icarus

Ok, perhaps make a page on the site to keep track
of the status.

>
>     2.  None will *not* be added to intbv.  An argument will
>         be added to the toVerilog and toVHDL to disable
>         "plain" Signal init and "memory" (array) init.
>         Something like the following.
>
>           toVerilog(... disable_init=False, disable_mem_init=False)
>           toVHDL( "" "" )

Arguments can always be used as ports, so configuration
should go elsewhere. Currently function attributes are for
such purposes:

toVerilog.disable_init = False


>     3.  toVerilog will only create initial values for Signals
>         converted to register types.

Yes, good compromise.

>
>     4.  Initial values for memories (list of signals) will be
>         generated.  If feasible the synthesizable versions [1]
>         of the memory init values will be generated.

More work, so we should be certain about synthesizability
certainly with Xilinx and Altera tools.

>
>
> Let me know if I missed something or summarized incorrectly.
>
> Regards,
> Chris
>
> [1] http://www.altera.com/literature/hb/qts/qts_qii51007.pdf
>
>
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