Re: [myhdl-list] MEP 107 assessment

[Jan D. <ja...@ja...>]

On 06/09/2012 09:41 PM, Christopher Felton wrote:
> <snip>
>>>
>>> 1) avoid the issue by using the interpreter
>>> to do the lookup outside of the generators
>>
>> Are there any limitations to this as far as referencing and assignment goes?
>>
>
> Best of my knowledge there are no restrictions.  You just have to follow
> the strict coding pattern to locally reference attributes.  The
> attributes can *not* be used in the generator (this is for the current
> conversion support, not the proposed).  I have been surprised with some
> of my recent experiments, though.

?

> Off topic, what do we call a function with generators that models
> hardware and potentially convertible.  In Verilog we have /module/ but
> that overlaps with Python /module/.  VHDL we have /entity/ and
> /architecture/ but it is not a similar enough to use one of those terms.
>    We don't want to use /function/ because it is too general.  What is
> the most appropriate term, /MyHDL function/?

I have addressed the terminology problem at the end of this
section in the manual:

http://www.myhdl.org/doc/current/manual/intro.html#parameters-and-hierarchy

As you can see, I think "module" is the right word, and if there
is ambiguity, use "MyHDL module".

I believe "module" is the generally accepted term in hardware design.
Verilog uses that word as the keyword, VHDL and MyHDL something else.
And of course, there is the complication that Python uses the keyword
to mean something different.

An advantage of using "MyHDL module" is that it doesn't refer to how
this is implemented exactly, which could be a function, method or class.



-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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