Re: [myhdl-list] MEP 107 assessment

[Tom D. <td...@di...>]

I think I may late joining in on this topic.

A couple of comments and a question below:

On 06/05/2012 03:52 PM, Jan Decaluwe wrote:
> I have read and thought about MEP 107. Here is my initial
> assessment.
>
> This MEP is strictly about conversion. This is explained in
> the first paragraph, but I think it should be mentioned in
> the title also, because this has proven to be an eternal source
> of confusion. It should be made clear that all modeling
> aspects being discussed are supported by MyHDL as it is today.
>
> One aspect of conversion is that it is unavoidable to consider
> the capabilities and restrictions of the conversion targets
> VHDL and Verilog, with special attention to synthesis. I think
> that aspect is taken into account insufficiently.
>
> Basically, the MEP proposes conversion support for various
> types of Signal object lookup. The example given is:
>
>       myObject.x.next = ListOfSignal[10] + DictOfSignal['fred']
>
> and the proposed conversion is:
>
>       myObject_x = ListOfSignal_10 + DictOfSignal_fred
>
> Conceptually, these 3 cases are very similar: lookup based on
> a manifest attribute name, index, string. The immediate question
> is why we would need support for 3 almost identical cases.
> The answer is that this example is not representative for
> the main purpose of a List or a Dict data structure.

I am not familiar with the current limitations for dicts, but if we used 
only the list would it not work? As long the list was defined properly 
and only used once since we consider them memories now. By using a 
constant, you would only ever be able to read one location from the 
memory. Probably not what you want.

What you would be trying to do is change how we use lists, I now 
consider lists as a memory when you try to covert them. But I suppose 
they could also be more of a register file, so that all locations could 
be used at the same time.

Obviously the structure of the HDL generated for the memory case vs the 
register file would need to be different. We had to code the list to 
memory specifically so synthesis would find them.

I personally don't think we need to be able to convert more types than 
is necessary to get the job done. So if you have to live with a certain 
coding style to get it to convert that is fine with me.

What are the advantages of lists and dicts as signal containers over 
classes?