Re: [myhdl-list] MEP : Signal Containers

[G. A. S. <g.a...@gm...>]

I've managed to read maybe 3/4 of the mail on this very long thread (and
think I understand the MEP since I did find an error in the example).
Somehow I got the idea that people aren't sure what value typical OO
features would have in a hardware environment, so are considering leaving
classes just a container for signals. Is that a correct assessment?  Or is
the problem that we don't know how to translate OO into verilog/vhdl?  If
its the former, I'd like to propose a couple of examples that would use OO
features and then you guys can pick them apart and tell me how its all
possible with myHdl today :-).

Cheers!
Andrew

On Fri, Jun 1, 2012 at 12:58 PM, Christopher Felton
<chr...@gm...>wrote:

> On 5/31/12 11:46 PM, G. Andrew Stone wrote:
> > Chris,
> >
> > In Example 1 of the MEP it says:
> >
> >   class  MyObj(object):
> >       def  __init__(self):
> >          x = Signal(intbv(0)[8:])
> >          y = Signal(intbv(0)[4:])
> >          z = Signal(intbv(0)[9:])
> >
> >
> > But I hope you mean:
> >
> >   class  MyObj(object):
> >       def  __init__(self):
> >          self.x = Signal(intbv(0)[8:])
> >          self.y = Signal(intbv(0)[4:])
> >          self.z = Signal(intbv(0)[9:])
> >
> > (addition of "self." to the variables)
> >
> > Or I will be VERY confused! :-)
> >
> > Cheers!
> > Andrew
> >
> >
>
> Yes, thanks for pointing out the error.  I have updated the MEP.
>
> Regards,
> Chris
>
>
>
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