Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/30/2012 06:20 AM, Christopher Felton wrote:

>
>>> py.test test_enums.py
> ============ test session starts ========== -- Python 2.7.3 --
> pytest-2.2.3 collected 6 items
>
> test_enums.py .F.F.. ... (lots-o-info)
>
> It runs 6 tests on 4 version of a similar design. The first two
> (TrafficOne and TrafficTwo), best of my knowledge, should simulate
> and convert. The second raises an error during conversion.
>
> The second failure is the issue briefly discussed where in a
> synchronous description conversion is successful where it should
> raise a ConversionError (because the converted code simulation will
> not match the MyHDL simulation).\

An interesting case. It is obvious here that the MyHDL is "invalid"
(simulation will certainly fail to prove that the design works).
The resulting VHDL would not even pass compilation, but the Verilog
will, because the abstract enum type is mapped to a low-level type,
resulting in a loss of type information.

In fact I should have spoken about a "valid" MyHDL simulation:
if the MyHDL can be "proven" to be invalid, then the resulting
conversion code is invalid also, even if conversion "works".

What I did in the 0.8-dev branch is to define the comparison
operators on enum items in more detail. Now the MyHDL design
should throw an exception on any meaningful simulation. The
conversion may still "work" but the MyHDL is clearly invalid.
(Although we need the (simulation) run-time to prove this,
as opposed to a static compilation phase.)

The changeset is in the public repo's.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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