Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 30/05/12 17:16, Jan Decaluwe wrote:
    . . .
> This is an error I had not seen so far from a failing test.
>
> Cause: a too restrictive test on permitted free var types
> in always_comb blocks. I have solved this in development.

Excellent, thanks, project sims & converts now.

Next I need to finish making sure that my memory model matches the 
Actel Igloo nano on chip block RAM, and find the simplest way to 
convert using a target macro.

Kind regards, Jan Coombs.
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