Re: [myhdl-list] TypeError: Unexpected type with toVerilog
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jandecaluwe
From: Jan D. <ja...@ja...> - 2012-05-30 16:17:21
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On 05/30/2012 11:44 AM, Jan Coombs wrote: > On 30/05/12 05:28, Christopher Felton wrote: > ... >> I modified your code so that it does not have the "undriven enum >> Signals". Once you remove the undriven enum Signals this example >> converts without throwing and error. > > I enthusiastically reverted the project code to use enums, but the error pattern there is still the same: > > In the async process which assigns an enum to the execNextState signal I get: > Object type is not supported in this context: ExST This is an error I had not seen so far from a failing test. Cause: a too restrictive test on permitted free var types in always_comb blocks. I have solved this in development. Workaround: put enum definitions in the outer scope (outside the def) Or use the development version, either branch. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |