Re: [myhdl-list] TypeError: Unexpected type with toVerilog
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From: Jan D. <ja...@ja...> - 2012-05-30 15:05:15
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On 05/30/2012 01:20 AM, Jan Coombs wrote: > On 29/05/12 20:53, Jan Decaluwe wrote: > . . . >> This is the hopefully clearer error message I just created >> in both branches. > Thanks, I like MyHDL like a long-lost friend, and hope to make much more progress together. > > Attached is simplified the test code, as there still seems to be a problem. Same problem: a undriven enum signal, not supported currently. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |