Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 30/05/12 05:20, Christopher Felton wrote:
    . . .
> The second failure is the issue briefly discussed where in a
> synchronous description conversion is successful where it should
> raise a ConversionError (because the converted code simulation will
> not match the MyHDL simulation).
>
> Unfortunately, this example has quite a bit of code. I didn't have
> the creative bug to generate a short-n-sweet version that covered
> all the items discussed in this thread.

I looked through your tests, and think that the short code I've 
just posted demonstrates a remaining failure mode.

Jan Coombs.