Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 30/05/12 05:28, Christopher Felton wrote:
    ...
> I modified your code so that it does not have the "undriven enum
> Signals". Once you remove the undriven enum Signals this example
> converts without throwing and error.

I enthusiastically reverted the project code to use enums, but the 
error pattern there is still the same:

In the async process which assigns an enum to the execNextState 
signal I get:
   Object type is not supported in this context: ExST

In all other processes in which execNextState or execState are 
referenced I get:
   Unexpected type for constant signal: execState
which probably relates exclusively to referencing enum constants.


What bothers me is that you fixed my code by adding a process which 
appears to have no relation to the enum errors reported.

I further refined this conclusion by making your code asynchronous, 
and only enabling the statements which are needed to avoid 
unassigned signals.  Your fix still converts, although, when 
testing enums, the only difference is that the code does not return 
an unassigned intbv.

Your fix further disturbs me, because the only effective debug 
process for conversion errors I have found is to disable 
simulation, and selectively remove offending code refs from the 
return statements.  This is the opposite of your fix, which adds 
apparently unrelated code.

If your corrected code represents a valid response, then all of my 
debug efforts may be invalid.

In the attached code I have eliminated the problems you corrected, 
and the sample now demonstrates failure to convert in code using 
enums, while matching code using simple constants is ok.

The sandboxed code is now closer to my project, but let me know if 
you want to see the the project - about 13.5kB at present.

Back to you(s), and back to real work now.

Jan Coombs.
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