[myhdl-list] Summary of "Intial Values Support" threads

[Christopher F. <chr...@gm...>]

We listed a summary a couple time but the initial value support (ivs) 
was embedded in a separate thread.  So, I thought it would be worth 
while to summarize in a new thread.


   1.  Initial value support can be re-enabled.  The Verilog
       support of initial values as verified with the latest
       of Quartus.
       Need to test with (list syn and sim tools)?
         [x] Quartus latest
         [ ] ISE (xst) latest
         [ ] cver
         [ ] icarus

   2.  None will *not* be added to intbv.  An argument will
       be added to the toVerilog and toVHDL to disable
       "plain" Signal init and "memory" (array) init.
       Something like the following.

         toVerilog(... disable_init=False, disable_mem_init=False)
         toVHDL( "" "" )

   3.  toVerilog will only create initial values for Signals
       converted to register types.

   4.  Initial values for memories (list of signals) will be
       generated.  If feasible the synthesizable versions [1]
       of the memory init values will be generated.


Let me know if I missed something or summarized incorrectly.

Regards,
Chris

[1] http://www.altera.com/literature/hb/qts/qts_qii51007.pdf