Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/29/2012 06:34 PM, Jan Coombs wrote:
> On 29/05/12 16:48, Jan Decaluwe wrote:
>      . . .
>> Then I suggest to use the development version (either the default
>> branch, which is the maintenance branch for 0.7, or 0.8-dev)
>> to see if anything changed or becomes clearer.
>
> Have just updated 0.8 and error is the same:
>
> raise ToVerilogError("Unexpected type for constant signal", s._name)
> myhdl.ToVerilogError: Unexpected type for constant signal: execState_E

This is the hopefully clearer error message I just created
in both branches.

For intbv or bool, supporting undriven signals is simple,
by assigning the constant initial value. There may be a
use for this, e.g driving some signals on an external
interface to a constant value if some features are not used.

But for enums it creates some complications in VHDL, and
I don't see how this could be useful. I expect that your
completed design will not have them.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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