Re: [myhdl-list] TypeError: Unexpected type with toVerilog
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From: Jan D. <ja...@ja...> - 2012-05-29 15:49:06
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On 05/29/2012 05:34 PM, Jan Coombs wrote: > On 29/05/12 08:45, Jan Decaluwe wrote: > >> Do you really have a need for undriven enum signals? > > The code was only for conversion testing, by changing the > commenting on the return lines. Perhaps I should have left it in > error display mode?:) > > I could expand the code in order to show simulation as well as > conversion, but wanted to save us both time. > > As far as I could see the enum error returned by this snippet is > the same as that from building my project, and using enums for the > state constants. Then I suggest to use the development version (either the default branch, which is the maintenance branch for 0.7, or 0.8-dev) to see if anything changed or becomes clearer. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |