Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/28/2012 5:20 AM, Jan Decaluwe wrote:
> On 05/26/2012 12:19 AM, Christopher Felton wrote:
>
>>
>> Again, the odd behavior is with the /always/ generator conversion.  I
>> believe, it created valid logic.  The converted code should simulate
>> correctly while the MyHDL code doesn't.
>
> That is meaningless. If the converted code doesn't simulate the same
> as the MyHDL code, there is a bug in the convertor, regardless of
> whether the result is deemed "correct" or not. (The same holds for
> synthesis, something almost nobody seems to understand.) The bug
> may be that the convertor did not refuse to convert.

Agree and agree should refuse to convert if possible.  Took me too long 
to realize the issue was an invalid use of the enum, thanks for the 
clarification.

>
>> This is *not* the error that I reported earlier, that the enum cannot be
>> used in an /always_comb/.
>
> To make progress, I need a simple (one-file) test that *fails*
> when I run it without me having to make any change (which could
> mask the problem you want address). I'll take it from there.
>

That was the original intent, it is that time management issue.  I will 
see what I can pull together in the next couple days.

Regards,
Chris