Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/26/2012 10:49 AM, Jan Coombs wrote:
> On 26/05/12 00:28, Jan Coombs wrote:
>> The /always_comb/ problem still shows in my processor code when
>> using enums, but converts ok when constants are used:
>
> The attached code shows a problem with using enum for state control
> inside an @always_comb process. I have carefully cut this down from
> my working code to show just my conversion problem.

I would be really surprized if this is your original
problem, because it is related to enum signals which
are not driven, unlikely to be useful in a real design.

Anyway, I have "solved" the problem reported in development
by raising error messages on the use of undriven enum signals.
Supporting this would be easy in Verilog, but not in VHDL,
at least not at the top-level, where enums create some
complications.

Do you really have a need for undriven enum signals?


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