Re: [myhdl-list] TypeError: Unexpected type with toVerilog
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From: Jan D. <ja...@ja...> - 2012-05-28 10:16:13
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On 05/26/2012 12:19 AM, Christopher Felton wrote: > > I don't know if if is really an incorrect use of the enums. I believe > most examples are to define an enum and then create a signal with the > enum type. > > tEnum = enum('One', 'Two', 'Three') > x = Signal(tEnum.One) > > The question is, should it be valid (convertible) to use enums as basic > constants? No, enum is in principle an abstract type for which the encoding could be chosen as part of later optimization. Note that you can choose between an number of encodings from myhdl (when defining the enum) or you can leave it to synthesis later (at least in VHDL where the enum is mapped to a VHDL enum). -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |