Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 25/05/12 23:19, Christopher Felton wrote:
[snip]
> This is *not* the error that I reported earlier, that the enum cannot be
> used in an /always_comb/.

I had hoped that the short tests I posted earlier would shed some 
light on this, but they only seem to demonstrate irregular case 
conversion.

The /always_comb/ problem still shows in my processor code when 
using enums, but converts ok when constants are used:

   if usingEnums:
     ExST = enum('Fetch1','Fetch2','NewAddr','Skip',  \
                     'Gap','Broken', encoding='one_hot')
     execState, execNextState =   \
                 [Signal(ExST.Fetch1) for i in range(2)]
   else:
     ExstFetch1,ExstFetch2,ExstNewAddr,ExstSkip,  \
                           ExstGap,ExstBroken = range(6)
     execState, execNextState =   \
                [Signal(intbv(0)[4:]) for i in range(2)]

The rest of the enum/const switch presently needs manual editing, 
but in summary, by process of elimination I have found that:

Assigning an enum to execNextState in an always_comb block produces 
the error:
   Object type is not supported in this context: ExST

In the clocked block which latches the next state, and in three 
other blocks where the state variable is compared with a constant, 
(ExST.xxx) this error is reported:
   TypeError: int() argument must be a string or a number, not 
'EnumItem'

Perhaps if I knew a little more of class notation I could have 
simple constants expressed in the same notation as enums, and 
simplify comparative testing.

Jan Coombs
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