Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/25/2012 4:45 PM, Jan Coombs wrote:
> On 25/05/12 22:22, Christopher Felton wrote:
>> On 5/25/2012 3:58 PM, Jan Decaluwe wrote:
>>> On 05/25/2012 02:54 PM, Christopher Felton wrote:
>> <snip>
>>
>>>
>>> How can key be defined, if the enum is defined inside the module?
>>
>> Good question, in the original example the enum was being used as
>> "constant" values.  And "key" was of type intbv.  The quick answer might
>> have been don't mix types?
>
> I didn't notice that until today, so fixed that, and posted two
> more samples.
>
> The original problem with enums was in some other code, so I will
> recheck that, and post a sample if the error has not been fixed.
>

I don't know if if is really an incorrect use of the enums.  I believe 
most examples are to define an enum and then create a signal with the 
enum type.

    tEnum = enum('One', 'Two', 'Three')
    x = Signal(tEnum.One)

The question is, should it be valid (convertible) to use enums as basic 
constants?

   tEnum = enum('One', 'Two', 'Three')
   b = intbv(1, min=0, max=10)
   b == tEnum.One

Regards,
Chris