Re: [myhdl-list] TypeError: Unexpected type with toVerilog
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jandecaluwe
From: Christopher F. <chr...@gm...> - 2012-05-25 22:19:53
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On 5/25/2012 4:22 PM, Christopher Felton wrote: > On 5/25/2012 3:58 PM, Jan Decaluwe wrote: >> On 05/25/2012 02:54 PM, Christopher Felton wrote: > <snip> > >> >> How can key be defined, if the enum is defined inside the module? > > Good question, in the original example the enum was being used as > "constant" values. And "key" was of type intbv. The quick answer might > have been don't mix types? > > The odd thing I ran into is that it worked in the /always/ generator and > not the /always_comb/. Below is the complete example, you should be > able to run it. > >> >> Can you or Jan C provide me with a short but complete example >> (including signal defs and conversion call) that fails? >> I'll start thinking after that :-) >> > This example for the most part is probably *bunk*. I thought I had extracted a portion of a larger example, which I might have. But the strange thing here isn't that the /always_comb/ didn't convert it is that the /always/ *did* convert. I got the cause and effect backwards. I would (should) have noticed this if I had created a test. def test(): clk = Signal(False) key = Signal(intbv(1, min=1, max=9)) led = Signal(intbv(0)[8:]) dip = Signal(intbv(0)[8:]) @always(delay(2)) def tb_clkgen(): clk.next = not clk @instance def tb_stimulus(): for ii in range(1,key.max): yield clk.posedge print("key %d led %d" % (key, led)) key.next = ii raise StopSimulation Simulation((tb_clkgen, tb_stimulus)).run() ------------- Output ------------- key 1 led 0 key 1 led 0 key 2 led 0 key 3 led 0 key 4 led 0 key 5 led 0 key 6 led 0 key 7 led 0 ------------- Again, the odd behavior is with the /always/ generator conversion. I believe, it created valid logic. The converted code should simulate correctly while the MyHDL code doesn't. This is *not* the error that I reported earlier, that the enum cannot be used in an /always_comb/. Regards, Chris |