Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/25/2012 3:58 PM, Jan Decaluwe wrote:
> On 05/25/2012 02:54 PM, Christopher Felton wrote:
<snip>

>
> How can key be defined, if the enum is defined inside the module?

Good question, in the original example the enum was being used as 
"constant" values.  And "key" was of type intbv.  The quick answer might 
have been don't mix types?

The odd thing I ran into is that it worked in the /always/ generator and 
not the /always_comb/.  Below is the complete example, you should be 
able to run it.

>
> Can you or Jan C provide me with a short but complete example
> (including signal defs and conversion call) that fails?
> I'll start thinking after that :-)
>

import myhdl
print myhdl.__version__
from myhdl import *

def case_ex1(clk, key, led):
     tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
     @always(clk.posedge)
     def hdl():
         if   key==tKey.UP:    led.next = 0xDE
         elif key==tKey.DOWN:  led.next = 0xCA
         elif key==tKey.LEFT:  led.next = 0xFB
         elif key==tKey.RIGHT: led.next = 0xAD
         else:                 led.next = 0x00

     return hdl

def case_ex2(key, led):
     tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
     @always_comb
     def hdl():
         if   key==tKey.UP:    led.next = 0xDE
         elif key==tKey.DOWN:  led.next = 0xCA
         elif key==tKey.LEFT:  led.next = 0xFB
         elif key==tKey.RIGHT: led.next = 0xAD
         else:                 led.next = 0x00

     return hdl

if __name__ == '__main__':
     clk = Signal(False)
     key = Signal(intbv(1, min=1, max=9))
     led = Signal(intbv(0)[8:])
     dip = Signal(intbv(0)[8:])

     print('Covert case_ex1')
     toVerilog(case_ex1, clk, key, led)
     toVHDL(case_ex1, clk, key, led)

     print('Convert case_ex2')
     toVerilog(case_ex2, key, led)
     toVHDL(case_ex2, key, led)


----------------
Output from run
----------------
   >> python case.py
   0.8dev
   Covert case_ex1
   Convert case_ex2
   Traceback (most recent call last):
     File "case.py", line 41, in <module>
       toVerilog(case_ex2, key, led)
_analyze.py", line 165, in _analyzeGens
     raise ConversionError(_error.UnsupportedType, n, info)
myhdl.ConversionError: File case.py, line 19: Object type is not 
supported in this context: tKey


Regards,
Chris