Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/25/2012 01:47 PM, Jan Coombs wrote:

>>
>> No, it was something else. Can you point me to the
>> post/author of the other problem(s). I lost track a little
>> but I will look into it with priority.
>
> Have attached short code sample. There was a problem using enums in @always_comb

Not short, and example fails with ImportError.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com