Re: [myhdl-list] TypeError: Unexpected type with toVerilog
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jandecaluwe
From: Jan D. <ja...@ja...> - 2012-05-25 11:10:18
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On 05/24/2012 10:53 PM, Christopher Felton wrote: > On 5/24/2012 3:23 PM, Thoma HAUC wrote: >> @always_comb >> def outputenable(): >> if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC) > > I believe this is the issue. There was a recent thread on this. It > looks like enums fail in an always_comb. A simple test case was > submitted recently. No, it was something else. Can you point me to the post/author of the other problem(s). I lost track a little but I will look into it with priority. Also, I propose to start using the bug tracker again, for formal bug reporting (after discussing it here preferably). Note that you can attach files to bug reports. I have done this for the bug that was just reported. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |