Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/24/2012 10:30 PM, Thoma HAUC wrote:
> Hi Jan,
>
> Are you able to print out the line number that raises the exception?
> Could you explain me what I did wrong?

I debugged this. You did nothing wrong - there was a bug
in case statement inference.

Workaround: use boolean tests on boolean variables
(if run, if not ack) for the moment.

Alternatively, I have fixed this in development, both
in the default maintenance branch as in 0.8-dev.

As a matter of style, it may be clearer to do all the
combinatorial decodes from a single always_comb, and
use default assignments in the begining, to specify
the most common value of a signal.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
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