Re: [myhdl-list] TypeError: Unexpected type with toVerilog
Brought to you by:
jandecaluwe
From: Thoma H. <tho...@gm...> - 2012-05-25 04:52:09
|
Hi Jan, The function name has evolved. I found the issue but I am not able to explain the reason. In fact, when I replace: elif (state == StateEnum.SEND): if (run == INACTIVE): state.next = StateEnum.SEND3 with: elif (state == StateEnum.SEND): if (run != ACTIVE): state.next = StateEnum.SEND3 the exception will not longer raise and the verilog description seems correct. Here are the source for the missing calls (visible in the traceback): def convert(converter, architecture): clr = Signal(ACTIVE) clk = Signal(INACTIVE) run, ack = [Signal(INACTIVE) for i in range(2)] serialin = Signal(HIGH) datain = Signal(intbv(0)[8:]) rdy = Signal(INACTIVE) oe = Signal(INACTIVE) serialout = Signal(HIGH) dataout = Signal(intbv(0)[8:]) converter(architecture, clr, clk, run, ack, serialin, datain, rdy, oe, serialout, dataout) def convert2verilog(architecture): convert(toVerilog, architecture) convert2verilog(bidir_serial_master) Thoma > > If Chris is right, that it is a top level interface problem, then you > will need to show the definitions for these: (clr, clk, run, > ack, serialin, datain, rdy, oe, serialout, dataout) in order for anyone > to re-create the problem, or to guesstimate it. > > Niggle: the name of this source does not seem to match the one shown in > your error messages. (convert2verilog(bidir_serial)) > > I am also struggling with this type of problem, so am very interested to > understand yours, and would like to try techniques that have sometimes > worked for me. > > For anyone to have a quick look they will need source that demonstrates > the problem with out having to re-create whatever might be missing. > > Jan Coombs |