Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 24/05/12 21:30, Thoma HAUC wrote:
    . . .
> Here is the python source:
    . . .
> def bidir_serial_master(clr, clk, run, ack, serialin, datain, rdy, oe,
> serialout, dataout):

If Chris is right, that it is a top level interface problem, then 
you will need to show the definitions for these: (clr, clk, run, 
ack, serialin, datain, rdy, oe, serialout, dataout) in order for 
anyone to re-create the problem, or to guesstimate it.

Niggle: the name of this source does not seem to match the one 
shown in your error messages. (convert2verilog(bidir_serial))

I am also struggling with this type of problem, so am very 
interested to understand yours, and would like to try techniques 
that have sometimes worked for me.

For anyone to have a quick look they will need source that 
demonstrates the problem with out having to re-create whatever 
might be missing.

Jan Coombs