Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Thoma H. <tho...@gm...>]

Hi Jan,

Are you able to print out the line number that raises the exception?
Could you explain me what I did wrong?

In advance many thanks

Here is the python source:

LOW, HIGH = bool(0), bool(1)
INACTIVE, ACTIVE = LOW, HIGH
StateEnum = enum('IDLE', 'HSYNC', 'SYNC', 'SYNC2', 'HADDR', 'ADDR', 
'ADDR2', 'ADDR3', 'HSEND', 'SEND', 'SEND2', 'SEND3', 'HRECV', 'RECV', 
'HRECV2', 'RECV2')

def bidir_serial_master(clr, clk, run, ack, serialin, datain, rdy, oe, 
serialout, dataout):

    state = Signal(StateEnum.IDLE)
    timeout = Signal(INACTIVE)
    count = Signal(intbv(0)[3:])
    inputreg = Signal(intbv(0)[8:])
    internaldata = Signal(intbv(0)[8:])
    int_rdy = Signal(INACTIVE)
    int_serialout = Signal(HIGH)

    @always_comb
    def copy():
        rdy.next = int_rdy
        serialout.next = int_serialout

    @always_comb
    def outputenable():
        if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC) or 
(state == StateEnum.SYNC2) or (state == StateEnum.HADDR) or (state == 
StateEnum.ADDR) or (state == StateEnum.ADDR2) or (state == 
StateEnum.ADDR3) or (state == StateEnum.HSEND) or (state == 
StateEnum.SEND) or (state == StateEnum.SEND2) or (state == 
StateEnum.SEND3)):
            oe.next = ACTIVE
        else:
            oe.next = INACTIVE

    @always_comb
    def ready():
        if ((state == StateEnum.IDLE) or (state == StateEnum.SYNC) or 
(state == StateEnum.ADDR) or (state == StateEnum.RECV2)):
            int_rdy.next = ACTIVE
        elif (state == StateEnum.SEND):
            int_rdy.next = run
        else:
            int_rdy.next = INACTIVE

    @always_comb
    def send_data():
        if ((state == StateEnum.ADDR) or (state == StateEnum.ADDR2) or 
(state == StateEnum.ADDR3) or (state == StateEnum.SEND) or (state == 
StateEnum.SEND2) or (state == StateEnum.SEND3)):
            int_serialout.next = internaldata[count]
        elif ((state == StateEnum.HADDR) or (state == StateEnum.HSEND) or 
(state == StateEnum.HRECV)):
            int_serialout.next = LOW
        else:
            int_serialout.next = HIGH

    @always(clk.posedge, clr.posedge)
    def storage():
        if (clr == ACTIVE):
            inputreg.next = 0
            internaldata.next = 0
        else:
            if ((ack == ACTIVE) and (int_rdy == ACTIVE)):
                inputreg.next = datain
            elif ((count == 7) and ((state == StateEnum.SYNC2) or (state 
== StateEnum.ADDR3) or (state == StateEnum.SEND2))):
                internaldata.next = inputreg
            if ((state == StateEnum.RECV) or (state == StateEnum.RECV2)):
                if (count == 7):
                    dataout.next[7:] = internaldata[7:]
                    dataout.next[7] = serialin
                else:
                    internaldata.next[count] = serialin

    @always(clk.posedge, clr.posedge)
    def counter():
        if (clr == ACTIVE):
            count.next = 0
            timeout.next = INACTIVE
        else:
            if ((state == StateEnum.SYNC) or (state == StateEnum.SYNC2) 
or (state == StateEnum.ADDR) or (state == StateEnum.ADDR2) or (state == 
StateEnum.ADDR3) or (state == StateEnum.SEND) or (state == 
StateEnum.SEND2) or (state == StateEnum.SEND3) or (state == 
StateEnum.RECV) or (state == StateEnum.RECV2)):
                count.next = (count + 1) % 8
            if (count == 6):
                timeout.next = ACTIVE
            if (count == 7):
                timeout.next = INACTIVE

    @always(clk.posedge, clr.posedge)
    def fsm():
        if (clr == ACTIVE):
            state.next = StateEnum.IDLE
        else:
            if (state == StateEnum.IDLE):
                if (run == ACTIVE):
                    state.next = StateEnum.SYNC
            elif (state == StateEnum.SYNC):
                if (ack == ACTIVE):
                    state.next = StateEnum.HSYNC
            elif (state == StateEnum.HSYNC):
                state.next = StateEnum.SYNC2
            elif (state == StateEnum.SYNC2):
                if (timeout == ACTIVE):
                    state.next = StateEnum.HADDR
            elif (state == StateEnum.HADDR):
                state.next = StateEnum.ADDR
            elif (state == StateEnum.ADDR):
                if (internaldata[0] == LOW):
                    state.next = StateEnum.ADDR2
                elif (ack == ACTIVE):
                    state.next = StateEnum.ADDR3
            elif (state == StateEnum.ADDR2):
                if (timeout == ACTIVE):
                        state.next = StateEnum.HRECV
            elif (state == StateEnum.ADDR3):
                if (timeout == ACTIVE):
                        state.next = StateEnum.HSEND
            elif (state == StateEnum.HSEND):
                state.next = StateEnum.SEND
            elif (state == StateEnum.SEND):
                if (run == INACTIVE):
                    state.next = StateEnum.SEND3
                elif (ack == ACTIVE):
                    state.next = StateEnum.SEND2
            elif (state == StateEnum.SEND2):
                if (timeout == ACTIVE):
                    state.next = StateEnum.HSEND
            elif (state == StateEnum.SEND3):
                if (timeout == ACTIVE):
                    state.next = StateEnum.IDLE
            elif (state == StateEnum.HRECV):
                state.next = StateEnum.RECV
            elif (state == StateEnum.RECV):
                if (timeout == ACTIVE):
                    if (run == ACTIVE):
                        state.next = StateEnum.HRECV2
                    else:
                        state.next = StateEnum.IDLE
            elif (state == StateEnum.HRECV2):
                state.next = StateEnum.RECV2
            elif (state == StateEnum.RECV2):
                if (ack == ACTIVE):
                    state.next = StateEnum.RECV
            else:
                state.next = StateEnum.IDLE

    return instances()

Thoma

> [texte cité caché]
_toVerilog.py",
> [texte cité caché]
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> [texte cité caché]



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