Re: [myhdl-list] Restrictions for conversion

[Jan D. <ja...@ja...>]

On 05/24/2012 06:27 PM, Norbo wrote:

> I completly agree with the 'X' but i am not so sure about the 'U'

Ok, but note that Verilog has only X, and MyHDL has to cater for
both :-)

In general, this type of problem is a real issue: we have to
support both HDLs at the back end, including their pecularities
and restrictions, and furthermore we poor open source guys have
take into account the restrictions of commercial tools!

> But i came to understand that the 'U' concept, kind of involves the 'X'
> concept
> and that the 'X' concept is not compatible with the intbv() integer
> concept, especially when
> it comes to operaters like "&" or "|".
>
> So in the end i kind of have to thank you for stopping me on continue
> implementing on something which is not reasonable feasible the way i
> thought.

Well, I think you were finding out that you know where you
start but you don't were you will end - I went through the
experience before.

Note that I haven't claimed that there is no issue - there is.
I also don't want to say categorically that "None" has no role
to play - I have used it for tristate representation. I only
said that supporting None in intbv is not a good idea.

In a situation like this, I think we should try to think out
of the box and innovate. Not try to mimic what exists,
because it's all broken in some way, but come up with
a better solution. I have some ideas but I need to think
a bit longer first.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com