Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/24/2012 1:43 PM, Thoma HAUC wrote:
> Hi Tom,
>
> I already simulated the design without any issue.
> The exception raises only during verilog generation process.
>
> Thoma
>
>> Not sure but have you simulated it in MyHDL? Usually that will help
>> expose problems better than trying to go directly to Verilog.
>>
>> On 05/21/2012 03:54 PM, Thoma HAUC wrote:
>>> Hi,
>>>
>>> I am new to myHDL and it seems to be a powerful tool.
>>> Today, I need some help to locate the reason of the below exception.
>>> Because there are no clue to indicate the line of the issue, I am
>>> currently blocked in my evaluation of myHDL.
>>>
>>> Thank you in advance.
>>>
>>> Thoma
>>>
<snip>
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 407, in _getNritems
>>>       raise TypeError("Unexpected type")
>>> TypeError: Unexpected type
>

This will be hard to assist with out an example, either the code you are 
trying to convert or a code example.  It possibly looks like an invalid 
type is being converted?

Regards,
Chris