Re: [myhdl-list] Restrictions for conversion

[Tom D. <td...@di...>]

On 05/24/2012 12:37 PM, Jan Decaluwe wrote:
> On 05/24/2012 06:14 PM, Tom Dillon wrote:
>>
>> On 05/24/2012 09:17 AM, Jan Decaluwe wrote:
>>> On 05/24/2012 04:14 PM, Christopher Felton wrote:
>>>> On 5/24/2012 9:02 AM, Tom Dillon wrote:
>>>> Use MyHDL :)
>>> Right :-)
>>>
>> So there are no Xs in MyHDL. Then what we are really talking about is
>> making sure the downstream tools don't put them in where they weren't?
>>
>> For instance, you have a state machine initialized to a known state in
>> MyHDL. How do you know the synthesis results to say an ASIC will produce
>> logic to match that?
> A formal check of flip-flop types inferred (fast, cheap, my preference),
> or gate level simulation, or formal verification of gate level against RTL.
>
> This would be identical to a pure VHDL flow, where the use
> of an enumerated type to specify states is standard practice.

I get it. I thought there was some kind of magic here that would keep 
you from having to verify your synthesis results and allow you to 
neglect good design practices up front.