Re: [myhdl-list] Restrictions for conversion

[Jan D. <ja...@ja...>]

On 05/24/2012 11:35 AM, Norbo wrote:


> I don't see a reason (other than irritating the VHDL or Verilog Simulation
> or synthesis tool) to write a initial value
> to a Signal that gets its value in a combinatorical process. Such a Signal
> gets its value at a beginning from a zero time delta cycle there
> is "time 0 missmatch" for such a signal.
>
> I also don't see whats this thing about the "time 0 mimatch".

The problem is that there may be an event in in Verilog/VHDL
while there may be no event in MyHDL. E.g. going from X->0
as opposed to 0->0.

This may lead to subtle difficulties, typically in test
benches. At least in mine.

> If i have a
> memory where the initial values are not written then i get a missmatch
> every time i read from the memmory wheater it is time 0 or time 5trillion.

This would be an argument to write the initial values.

> The only missmatch i see is from a Flip-Flop output signal. In this case i
> think the missmatch is a good thing, because it allows to check if a
> Flip-Flob is not
> not reseted.

This has been covered before: at best it is a half-hearted
solution for which much better formal alternatives are
available.

Some background perhaps: the type system in MyHDL was not inspired
by Verilog, but by VHDL, in particular its abstract types such as
integer, boolean and enum. The simple reason is that I largely
prefer such types over low-level "representational" types such
as signed/unsigned or the Verilog types.

In particular, intbv is intended to be a better constrained
integer type: with indexing support and without limits on the
constraints. However, it keeps the fact that abstract types
are initialized to some implicit or explicit value that
belongs to the type.

And again, there is also bool and enum whose use I would like
to encourage in synthesizable MyHDL.

I have also given considerable thought on the value of
'X' in digital design. A full explanation is very extensive,
but my conclusion is that 'X' has no place in RTL design,
and its value at the gate level is doubtful at best.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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