Re: [myhdl-list] Restrictions for conversion

[Norbo <Nor...@gm...>]

Am 23.05.2012, 04:37 Uhr, schrieb Christopher Felton  
<chr...@gm...>:


> That was somewhat missed phrased, "... reasonable method ...".
> Currently initial values are not supported (enabled), for basic types or
> arrays (memories).  Currently you cannot do either.  I should have
> said, pre-init RAM is not supported in MyHDL.
>
> Known, reasonable, RAM pre-init methods are available for Verilog/VHDL.
>   It seems reasonable to include with the initial value support.
>
> Norbo prototyped this and it all seemed good but we have been discussing
> the overall behavior.  I think this is where we sit right now.
>
>     1.  Initial value support should be added, it resolves
>         the time 0 mismatch.  It has been verified with
>         the latest versions of Quartus and ISE.

I don't see a reason (other than irritating the VHDL or Verilog Simulation  
or synthesis tool) to write a initial value
to a Signal that gets its value in a combinatorical process. Such a Signal  
gets its value at a beginning from a zero time delta cycle there
is "time 0 missmatch" for such a signal.

I also don't see whats this thing about the "time 0 mimatch". If i have a  
memory where the initial values are not written then i get a missmatch
every time i read from the memmory wheater it is time 0 or time 5trillion.

The only missmatch i see is from a Flip-Flop output signal. In this case i  
think the missmatch is a good thing, because it allows to check if a  
Flip-Flob is not
not reseted.

greetings
Norbo